The invention relates in general to memory devices, and more particularly, to volatile memory devices and methods for forming the same.
A dynamic random access memory (DRAM) device is a typical volatile memory device for integrated circuit devices. A DRAM cell includes an access transistor and a storage capacitor. A buried strap has been employed in fabricating deep trench-based DRAM devices. The buried strap is critical in connecting the storage capacitor to the access transistor. Accordingly, the resistivity of the buried strap and the buried strap width are important factors in providing superior interconnect properties between transistors and capacitors. The buried strap width is subject to the active area of the deep trench overlay.
FIG. 1 is a cross-section showing a conventional deep trench-based DRAM structure. The DRAM structure includes a substrate 100 having a plurality of pairs of neighboring trenches formed therein. A pair of neighboring trenches 101 is shown for simplicity. Two buried trench capacitors 105 are respectively disposed in a lower portion of each trench 101. The capacitor 105 includes a buried bottom plate 102 formed in the substrate 100 around the lower portion of the trench 101, a top plate 104 disposed in the lower portion of the trench 101, and a capacitor dielectric layer 103 disposed between the buried bottom plate 102 and the top plate 104. Two collar oxide layers 106 are respectively disposed over an upper portion of the sidewall of each trench 101, and two first conductive layers 108 are respectively disposed in the upper portion of each trench 101 and surrounded by the collar oxide layers 106. Two second conductive layers 110 are respectively disposed overlying the collar oxide layer 106 and the first conductive layer 108 in each trench 101. A shallow trench isolation (STI) structure 112 is disposed between the neighboring trenches 101 to serve as an isolation region between the buried trench capacitors 105. Access transistors 114 are disposed overlying the substrate 100 beyond of the pair neighboring trenches 101, which includes a gate 114, a gate dielectric layer 113, and a source/drain region 115. Two gates 117 are respectively disposed on the STI structure 112 over each trench 101.
FIG. 2 is a plan view of the pair of neighboring trenches before formation of the STI structure in FIG. 1. Conventionally, in order to leave a space for forming the STI structure, an island photoresist pattern is used for defining the active area AA. Due to device shrinkage, misalignment is likely to occur when aligning the active area AA to the trench 101. Consequently, process windows are narrow, and shorts between the active area AA and the trench capacitor 101 are more serious.